signal-integrity

AI coding agent skills for KiCad electronics design. Works with Claude Code and OpenAI Codex. Analyze schematics, review PCB layouts, EMC pre-compliance, SPICE simulation, download datasheets, source components, and prep boards for fabrication.

Python tools for signal integrity applications

🤖 Intelligent AI-powered PCB design automation tool using machine learning for component placement, routing optimization, and signal integrity analysis. Supports KiCad, Altium Designer, and Eagle CAD integration.

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPGA makers on limited budget. Augments openXC7 CI/CD, challenging its timing-savvy. Promotes the lesser-known EU boards.

A Python implementation of signal-power integrity co-analysis framework for inter-chiplet links.

USB 3.2 Gen 1 4-port hub based on TI TUSB8044A. 6-layer impedance-controlled PCB with USB-C cold-socket compliance, hardware power sequencing, and no MCU.

🧠 Claude Code Skill — Full-stack PCB design assistant for embedded/IoT. 23 design modules covering schematic, layout, DFM, EMC, RF, thermal, compliance & production. Pairs with 立创 EDA & KiCad.

USB SuperSpeed 3.1 → Gigabit Ethernet adapter (Microchip LAN7800) with USB-C female and USB-A male connectors

A pure-Python parser for IBIS (.ibs) files — extracts I/O buffer model data including pin, component, and waveform information from standard-cell and pad libraries for EDA signal integrity workflows.

Interactive PAM4 reference-receiver filter explorer for PCIe Gen6, IEEE 802.3ck, and IEEE P802.3dj. Runs entirely in the browser with Voici, JupyterLite, and Pyodide.

Co-Founder, Michvi LLP | Design-time governance, signal integrity, structural risk

1D telegrapher's-equation experiment: source-series-termination resistor on a microcontroller output. Third book of lab-pcb-physics.

Digital Signal Governance (DSG) conceptual framework for signal integrity and digital governance.

Physics-backed virtual SerDes instrument bench for PAM4, optical links, DCA, BER, DSP and FEC.

Signal & Power Integrity lab — eye 312mV, 50Ω/100Ω, crosstalk -35dB, PDN <10mΩ (Saturn/LTspice)

Static timing analysis with signal integrity — WNS/TNS sign-off gate, SI/crosstalk + statistical OCV.

USB 3.0 High-Speed PCB Signal Integrity Design

Datasheet and Touchstone to validated S2P, SPICE and engineering models with vector fitting, passive RLC synthesis and a PyQt5 GUI.

PCB design desktop app: interactive editor, AI (Ollama), DRC, power/thermal/SI analysis, stackup editor, BOM, netlist, JLCPCB export, STL/STEP enclosure generator

LTspice simulation and mitigation of severe EMI on an EV CAN bus. Compares Shielded Cable and RC Low-Pass Filter approaches to suppress 100V motor transients, achieving <100mV common-mode noise and ensuring ≤ 10⁻⁹ BER.