bluespec

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

Connectal is a framework for software-driven hardware development.

P4-14/16 Bluespec Compiler

RISC-V BSV Specification

Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.

Bluespec SystemVerilog extension for VS Code

Bluespec System Verilog language extension for Visual Studio Code

Implementation of Vector Reduce Min and Vector Negation ASIC Hardware, plus a toy CPU, memory and custom ISA for demo. Can be compiled to Verilog. Demos include fib series computations using custom ISA (and custom assembly) and some vector programs.

Implementation of proposed RISC-V xbitmanip instructions in BlueSpec

Flame thrower is a on-chip network router written in bluespec system verilog

To toy around with Bluespec-SystemVerilog and my Basys3 board

Collection of projects using Verilog and Bluespec on the Spartan Edge Accelerator FPGA Board

Bluespec SystemVerilog implementation of the Keccak primitive (SHA-3)

Low-cost modular acquisition and stimulation system for neuroscience

📚️ A repository for showcasing my knowledge of the BlueSpec programming language, and continuing to learn the language.

⌨️ The BlueSpec programming language IDE submodule for SNU Programming Tools (2D Mode)

Ook!-interpreter in Bluespec System Verilog